(a) Field of the Invention
The present invention relates to a negative resistance circuit, and more particularly, to a negative resistance circuit composed of a plurality of field effect transistors (FETs) and suitable for integration into IC chips.
(b) Description of Related Art
Over the years, various negative resistance devices from Esaki diodes to resonant tunneling diodes have been developed. If a negative resistance circuit including such a negative resistance device was used for memory circuits or flip-flop circuits integrated in IC chips, the number of elements in these circuits could be reduced, thereby enabling to make these circuits smaller. Such negative resistance circuits would in turn facilitate implementation of multivalued logic circuits, which could be used to form various circuits having new functions.
Negative resistance devices as mentioned above, however, have not been actually used in IC chips, because the process for manufacturing negative resistance devices differs from that of bipolar transistors or FETs integrated in the IC chips. Additionally, resonant tunneling diodes have a difficulty in obtaining a negative resistance characteristic operable at room temperature. An attempt has been made to obtain a circuit having a negative resistance characteristic by using therein semiconductor elements of bipolar transistors or FETs without a negative resistance device. An example of such a circuit is described in "The Transactions of The Institute of Electronics, Information and Communication Engineers", vol. J68-C, p.43, January, 1985.
Referring to FIG. 1A, the negative resistance circuit described in the above document has a structure in which a P-channel depletion FET 15 and an N-channel depletion FET 16 are connected in series between negative resistance ports 20 and 30 of the negative resistance circuit, with their drains connected with each other. The gate electrode of each one of the depletion FETs 15 and 16 is connected to the source electrode of the other of the FETs 15 and 16. When a supply voltage applied between the negative resistance ports 20 and 30 is close to zero, both the P-channel depletion FET 15 and the N-channel depletion FET 16 are in ON states.
If the supply voltage applied between the negative resistance ports 20 and 30 is gradually increased, the gate-source voltage of the P-channel depletion FET 15 becomes negative while the gate-source voltage of the N-channel depletion FET 16 becomes positive, so that the drain current flowing through both the P- and N-channel depletion FETs 15 and 16 decreases. Due to this function, the circuit of FIG. 1A exhibits a negative resistance characteristic in which current flowing between the negative resistance ports 20 and 30 decreases when the supply voltage increases between the negative resistance ports 20 and 30.
Depletion FETs are generally used for implementing a negative resistance circuit. However, enhancement FETs can be used in negative resistance circuit, as disclosed in Japanese Patent Laid-Open Publication No. 1(1989)-58693. Referring to FIG. 1B, the negative resistance circuit of this type comprises a P-channel FET 17 and an N-channel FET 18, and the N-well of the P-channel FET 17 is connected to the drain electrode of the N-channel FET 18, while the P-well of the N-channel FET 18 is connected to the drain electrode of the P-channel FET 17. The source electrode and the gate electrode of the P-channel FET 17 are connected to a first negative resistance port 20 and a first control port 50, respectively, while the source electrode and the gate electrode of the N-channel FET 18 are connected to a second negative resistance port 30 and a second control port 60, respectively.
In the negative resistance circuit shown in FIG. 1B, a control voltage is supplied to the second control port 60 relative to the second negative resistance port 30. The level of the control voltage is maintained between a first threshold voltage of the N-channel FET 18 in the state where the electric potential at the P-well of the N-channel FET 18 is equal to that of the source electrode of the N-channel FET 18 and a second threshold voltage of the N-channel FET 18 in the state where the electric potential at the P-well of the N-channel FET 18 is lower than that of the source electrode of the N-channel FET 18.
Another control voltage is supplied to the first control port 50 relative to the second negative resistance port 30. The level of this control voltage is maintained between a first threshold voltage of the P-channel FET 17 in the state where the electric potential at the N-well of the P-channel FET 17 is equal to that of the source electrode of the P-channel FET 17 and a second threshold voltage of the P-channel FET 17 in the state where the electric potential at the N-well of the P-channel FET 17 is higher than that of the source electrode of the P-channel FET 17.
In order to shift the negative resistance circuit of FIG. 1B from an OFF state to an ON state, at least one of the FETs 17 and 18 is turned on by adjusting one or both of the control voltages supplied to the first and second control ports 50 and 60. Also, the circuit can be turned ON by increasing the voltage supplied between the first and second negative resistance ports 20 and 30 by such an amount that makes it possible that the drain-source voltage of one of the FETs 17 and 18 exceeds its breakdown voltage and lets the drain current of the one of the FETs flow into the well of the other of the FETs.
In order to shift the circuit of FIG. 1B from an ON state to an OFF state, the current flowing between the negative resistance ports 20 and 30 is reduced to zero by reducing the voltage between the negative resistance ports 20 and 30 down to zero, or one or both of the FETs 17 and 18 is turned off by adjusting one or both of the control voltages supplied to the control ports 50 and 60.
With the conventional negative resistance circuits as described above, there is a drawback in that the entire circuits cannot be formed of FETs of the same conductivity type, which means that a negative resistance circuit cannot be formed in an IC chip of an N-channel MOSFET, an ECL (emitter coupled logic) or a DCFL (direct coupled field effect transistor logic) including a GaAs (gallium arsenic) FET all formed of semiconductor elements of a single conductivity type.